1. Field of the Invention
The present invention relates to a timing signal generating apparatus for generating timing signals asynchronously with a reference signal.
2. Description of the Prior Art
For having a better understanding of the present invention, description will be made on the hitherto known relevant technique in some detail. FIG. 2 of the accompanying drawings shows a typical one of the conventional timing signal generating apparatus. In the figure, a reference numeral 1 denotes a controller, 2 denotes a signal generator, 3 denotes a memory and a numeral 4 denotes a counter. The controller 1 supplies an address signal 11 to the signal generator 2 and the memory 3. In response, the signal generator 2 produces a reference signal 12 which provides a basis for a test cycle. The counter 4 counts the content of data read out from the memory 3 in response to the address signal 11 from the controller 1, starting from the rise-up of the reference signal pulse 12, and produces a timing signal 14 at the output thereof. Consequently, the timing signal 14 undergoes an amount of delay which corresponds to the time required for the counter 4 to count the data content read out from the designated address of the memory 3. In this manner, a number of discrete timing signals 14 can be derived which number corresponds to that of the data contents stored in the memory 3.
FIG. 3 of the accompanying drawings shows waveforms or sequences of signals making appearance at various circuit points of the arrangement shown in FIG. 2. More specifically, FIG. 3 shows at (a) the address signal 11 produced by the controller 1, wherein address A1 and A2 are indicated, by way of example. FIG. 3(b) is a waveform diagram of the reference signal 12 produced by the signal generator 2, in which reference pulses P1 and P2 are shown. FIG. 3(c) shows the data 13 stored in the memory 3, which data includes data contents D1 and D2, as will be seen. More specifically, the data content D1 is stored in the memory 3 at the address A1, while the data content D2 is located at the address A2 of the memory 3.
Turning to FIG. 2, the counter 4 is loaded with the content D1 of data 13 in synchronism with the pulse P1 of the reference signal 12. Subsequently, the data content D2 is loaded in the counter 4 in synchronism with the timing pulse P2.
FIG. 3 shows at (d) the timing signals 14 outputted by the counter 4 and containing pulse T1 and T2, respectively. It will be seen that the timing signal pulse T1 is produced with a delay relative to the rise-up of the reference signal pulse P1, which delay corresponds to the time required for the counter 4 to count the data content D1 of the data 13. On the other hand, the timing signal pulse T2 is delayed relative to the rise-up of the reference signal pulse P2 for a time required for counting the data content D2. In this connection, it is assumed that the data content D1 represents "100". Then the timing signal pulse T1 is produced after the counter 4 has counted "100". Further, assuming that the data content D2 represents "150", the timing signal pulse T2 is produced when the counter 4 has made 150 counts. In this way, with the arrangement of the hitherto known timing signal generating circuit shown in FIG. 2, the pulses T1 and T2 are produced as the timing signals 14 with delays relative to the reference signal 12 which correspond, respectively, to the times taken for counting the data contents D1 and D2 stored in the memory 3.
It is however noted that the amount of data capable of being stored in the memory 3 is finite, which in turn means that difficulty is encountered in producing a large variety of timing pulse signals 14 (T1,T2) having periods differing from that of the reference signal 12.
Some of the memories implemented in the form of IC (integrated circuit) is provided with an additional input or enable terminal for the purpose of allowing information or data to be read out from the IC memory at high speed with high efficiency in addition to the conventional write-in and read-out enable terminals. In such memory device, test is often conducted for checking the mutual influence between the two read-out enable terminals. To ths end, a timing clock is applied to the additional enable terminal which is utterly independent of the timing signal applied to the other conventional read-out enable terminal. In that case, a timing signal generating apparatus is additionally required for generating the timing signal having a period which can vary within a predetermined range in addition to the conventional timing signal generator inherently designed for the test in concern.
The number of the various timing signals can naturally be increased by correspondingly increasing the oscillation frequency of the signal generator 2 and the capacity of the memory 3. In that case, however, problem will arise in that a large amount of data has to be loaded in the memory 3 in precedence to the test, being undesirably accompanied with the increased number of addresses 11, whereby the control procedure becomes correspondingly complicated, to another disadvantage.